Open-Source ASIC Initiative
AltASIC develops a fully open-source, Verilog-based ASIC implementation of the classic CryptoNight proof-of-work algorithm — published openly for the community to inspect, verify, and build on.
Who We Are
AltASIC is an open-source hardware and cryptocurrency ASIC development initiative dedicated to building a fully public, auditable implementation of the CryptoNight proof-of-work algorithm at the silicon level.
Rather than locking designs behind proprietary walls, we publish our Verilog source so anyone can read it, verify it, and build on it. CryptoNight was designed with ASIC-resistance in mind, and we believe the fairest way to explore that frontier is in full public view.
We work as a distributed group of hardware engineers, RTL designers, and cryptocurrency contributors collaborating openly on architecture, verification, and documentation.
Every line of RTL is published publicly under an open license.
Built around the memory-hard scratchpad and AES mixing rounds.
Open issue tracking and public testbenches at every stage.
Documentation written to help new contributors get involved.
Co-Founders
AltASIC was co-founded to bring transparency to ASIC development for memory-hard proof-of-work algorithms, pairing hardware design experience with deep cryptocurrency community roots.
Co-Founder
Focused on community coordination, project direction, and growing the open-source contributor base around the CryptoNight ASIC effort.
Co-Founder
Leads hardware architecture and the Verilog implementation of the CryptoNight algorithm, alongside verification and documentation.
The Technology
A hardware implementation of the classic CryptoNight algorithm, including its memory-hard scratchpad and AES-based mixing stages.
The full design is written in Verilog and openly available, so contributors can review, simulate, and extend it directly.
Public simulation environments confirm correctness against reference CryptoNight implementations.
Early-stage FPGA bring-up validates the design in real hardware ahead of custom silicon.
Architecture notes and module-level documentation published alongside the code.
Issues, pull requests, and design discussions happen openly, welcoming engineers and miners alike.
Project Roadmap
Documenting CryptoNight in detail to establish a shared reference for the implementation.
Defining the compute and memory architecture needed for the scratchpad and mixing stages.
Writing and publishing the open-source RTL, with ongoing community review.
Deploying on FPGA hardware to confirm correctness and gather performance data.
Expanding contributors and exploring a path toward custom silicon.
Why Open Source
Every Verilog module is open for anyone to read and verify.
The design starts from CryptoNight's memory-hard structure.
No single party controls the roadmap or the code.
All RTL and verification assets are released openly to fork and extend.
Get In Touch
Whether you're a hardware engineer, a Verilog hobbyist, or just curious about CryptoNight ASIC development, we'd love to hear from you.